Semiconductor devices require a suitable operation voltage according to the characteristics thereof. With continuous advancement in developing device technologies to reduce power consumption, internal voltages have been reduced. However, there may be a need for devices or logic circuits operable at relatively high voltages. Flash memory devices, for example, may need high writing and/or erasing voltages. High voltage transistors may thus be integrated into flash memory devices to supply such a high voltage to a cell array and/or to pump a low voltage up to a high voltage.
A junction of a high voltage transistor may be formed using an LDD (lightly doped drain) structure or a DDD (double doped drain) structure. There may be limits to manufacturing more highly integrated devices capable of resisting high voltages using such junction structures. If the depth of a low-concentration diffusion layer is reduced for the purpose of overcoming a short-channel effect, for example, a junction breakdown between a high-concentration diffusion layer and a substrate may result. If a concentration distribution of a high-concentration diffusion layer is alleviated to overcome junction breakdown, an effective area of the high-concentrated diffusion layer may increase.
An elevated source/drain technology has thus been developed with an epitaxial layer being formed on a substrate and impurities being implanted into the epitaxial layer. Korean Patent Publication No. 2001-109783 and U.S. Pat. No. 6,087,235 disclose methods of fabricating a transistor with an elevated source/drain structure being formed using selective epitaxial growth. FIGS. 1 through 3 are cross-sectional views illustrating a conventional method of fabricating a transistor.
Referring to FIG. 1, in the conventional transistor, a field isolation film 121 is formed in a semiconductor substrate 102 to define an active region. A gate insulation layer 302 is formed on the active region, and a conductive gate layer 304 is formed on the gate insulation layer 302. A capping layer 309 is formed on the gate layer 304. A drain diffusion region 306 and a source diffusion region 308 are formed by implanting impurities into the semiconductor substrate 102 at opposite sides of the gate layer 304. First spacers 310 are formed at sidewalls of the gate layer 304. Elevated drain and source contact structures 314 and 316, having a drain facet 318 and a source facet 320 respectively, are formed on the semiconductor substrate 102 beside the first spacers 310.
Referring to FIG. 2, second spacers 330 are formed at both sides of the gate layer 304, covering the source facet 320 and the drain facet 318. The capping layer 309 is etched away from the gate layer 304. Impurities are implanted into the elevated drain contact structure 314 and the elevated source contact structure 316. Portions of the substrate 102 adjacent to the gate layer 304 may be shielded from the implanted impurities by the second spacers 330.
Referring to FIG. 3, a drain silicide layer 340 is formed on the elevated drain contact structure 314, a source silicide layer 342 is formed on the elevated source contact structure 316, and a gate silicide layer 344 is formed on the elevated gate contact structure 304. An inter-level insulation layer 354 is deposited on the resultant structure for electrical isolation of components of the transistor 300. Next, drain and source contacts 350 and 352 are formed to provide connections to the drain and source silicide layers 340 and 342 passing through the inter-level insulation layer 354.
In the conventional transistor architecture described above, the impurity implantation is performed to dope the elevated drain contact structure 314 and the elevated source contact structure 316 to form a drain region and a source region. Accordingly, the source and drain low-concentration diffusion regions may be shallowly formed on the substrate to reduce short-channel effects. Further, since the second spacers 330 cover the source and drain facets 320 and 318 and the high-concentration impurities are implanted into the elevated drain and source contact structures, an impurity layer may not be formed deeply in lower portions of the source and drain facets 320 and 318. A silicon layer, however, may be grown with crystallization between the gate layer and the impurity layer. Thus, when a high voltage is applied to the source contact or the drain contact, an electric field may be exerted on the silicon layer between the gate layer and the impurity layer. More particularly, when a voltage of 10 to 20 volts or higher is applied to the source contact or the drain contact, the voltage may be provided through the silicon layer to cause an increase of a gate potential. An increase of the gate potential due to a source or drain voltage may thus be reduced by enlarging a thickness of the gate spacer. There may be limits, however, to extending thicknesses of gate spacers in highly integrated circuit devices.